FMC boards (old)

FMC-141FMC-142FMC-902FMC-904

Single/Dingual 2.3GHz 500/400MSps 12/14b ADC

FMC-141 is an advanced high-speed ADC board. It contains one or two A/D converters (500MSps/12-bit or 400MSps/14-bit), featuring extremally wide analog front end bandwidth of 2.3 GHz. The parallel digital LVDS output interface supports FPGA Mezzanine Card FMC-LPC connector standard. The optional LF analog paths (switched with relays) may be provided on demand.

Clocking resources provide users a selection of onboard sample clock frequencies. With an onboard oscillator user may select sample rates of 340, 400, 420 and 500 MSps (or another set of frequencies on demand). The onboard programmable clock buffer allows generation of derivative clock frequencies, as well as controll of the clock phases for multi-phase signal sampling mode. For the extremally precise timing the external clock may be also provided. The board is equipped with external clock input and output connectors. Thus the number of input channels may be easily increased by synchronizing multiple boards.

Trigger In and Trigger Out signals on front panel MMCX connectors are passed directly to/from the host FPGA via balanced transmission lines.

The board is also equipped with a set of miscellaneous functions: 4 digital 2.5V I/Os and 4 digital 3.3V I/Os, 3 LEDs, control resources for analog paths (relays and power-up signals), clock oscillator frequency selector, clock buffer control (frequency, phase, power-up, synchro-start and others) – all controlled via SPI interface by the host FPGA.

 


Board Specification

Basic Specification

  • Conversion channels: 1 or 2
  • Sampling frequency: up to 500 Msps (single channel) / up to 1000Msps (interleaved)
  • Sampling resolution: 12-bit / 14-bit
  • Devices: 2x TI’s ADS5463 / ADS5474
  • Analog inputs: main HF (auxiliary LF – optional, switched by signal realys)
  • THD (board): 74 dBc
  • SFDR (board): 76 dBc

 

Main Analog Inputs (HF)

  • Input connectors: single-ended, front MMCX
  • Input impedance: 50 Ohm, AC coupled
  • Input bandwidth (3dB): >1.6 GHz
  • Full scale input voltage: 1.8V pk-pk (9 dBm)

 

Auxiliary Analog Inputs (LF, optional)

  • Input connectors: single-ended, front MMCX
  • Input impedance: 50 Ohm, AC coupled
  • Input bandwidth (3dB): TBD
  • Full scale input voltage: TBD
  • Amplifier power-up: host FPGA controlled via SPI

 

Clock and Trigger Signals

  • Internal clock, software selectable (host FPGA controlled via SPI): 680 / 800 / 840 / 1000 MHz
  • Clock distribution: CDCE18005 programmable buffer (host FPGA controlled via SPI)
  • External clock input: 50 Ohm, single-ended, AC coupled, front MMCX
  • External clock input frequency: up to 1000 MHz
  • External clock input level: TBD
  • External clock output: 50 Ohm, single-ended, AC coupled, front MMCX
  • External clock output frequency: up to 1000MHz (default – half the input clock frequency)
  • Trigger input: 50 Ohm, single-ended, LVDS buffered to host FPGA
  • Trigger output: 50 Ohm, single-ended, LVDS buffered to host FPGA

 

Miscellaneous

  • Host FPGA connector: FMC-LPC
  • Digital I/Os: 4 single-ended 3.3V LVCMOS I/Os & 4 single-ended 2.5V LVCMOS I/Os (optional)
  • Auxiliary clocks: single-ended 3.3V LVCMOS input & output
  • LEDs: red, green, blue (host FPGA controlled via SPI)

 

Power & Dimensions

  • External power supply (required): 5.5V, Molex MX-5267-04A 2.5mm pitch SPOXTM vertical wire-to-board header
  • Power consumption (main analog inputs):
  • 1 channel: 5.4W
  • 2 channels: TBD
  • Dimensions: 69.0 × 95.0 mm

 

Support

  • Vivado Interface IP
  • Host FPGA Pin Description (UCF/XDC)

Ordering

FMC-141-n-fbb-in

  • n – # of channels/ADCs: 1 or 2
  • fbb – frequency/bits: 512 for ADS5463 (500Msps/12bits) or 414 for ADS5474 (400Msps/14bits)
  • in – type of inputs: H for High Frequency or HL for High and Low Frequency

Examples

  • FMC-141-1-512-H
  • FMC-141-2-414-HL

Performance

All maesurements were taken with Crystek’s CCSO-914X-1000 Ultra-Low Phase Noise 1GHz SAW Clock Oscillator driving the external clock input.

Quad 1Msps 20b ADC
Quad 1Msps 16b DAC
Single 2.3Ghz 500Msps 12b ADC

FMC-142 is a multi-purpose ADC/DAC board. It contains nine converters: four high-precision D/A converters (16-bit/1Msps), four high-precision A/D converters (20-bit/1Msps) and one optional fast A/D converter (500Msps/12-bit or 400Msps/14-bit, featuring extremally wide analog front end bandwidth of 2.3 GHz). The digital LVCMOS 2.5V and LVDS interfaces support FPGA Mezzanine Card FMC-LPC connector standard.

Clocking resources provide perfect synchronization to all the converters. The external clock source is required. The onboard programmable clock buffer allows generation of derivative clock frequencies and controll of the clock phases. The board is equipped with external clock input and output connectors. Thus the number of input channels may be easily increased by synchronizing multiple boards.

Auxiliary Trigger In and Trigger Out signals on MMCX connectors are passed directly to/from the host FPGA via balanced transmission lines.

The board is also equipped with a set of miscellaneous functions: 4 digital 2.5V I/Os and 4 digital 3.3V I/Os, 3 LEDs and control resources for clock buffer (frequency, phase, power-up, synchro-start and others) – all controlled via SPI interface by the host FPGA.


Board Specification

Basic Specification

  • Conversion channels: 9
  • Sampling frequency: up to 1 Msps for high-precision converters / up to 500 Msps for high-speed converter
  • Sampling resolution: 16/20 bits for high-precision converters / 12 bits for high-speed converter
  • Devices: 4x LTC2642 / 4x LTC2378 / 1x ADS5463 (optional)
  • Analog inputs/outputs: 4 HP outpurs (SDAC) / 4 HP inputs (SADC) / 1 HF input (FADC) – optional
  • THD (board): TBD
  • SFDR (board): TBD

 

 

 

High-Precision Analog Outputs (SDAC)

  • Input connectors: single-ended, front MMCX
  • Input impedance: 50 Ohm, DC coupled
  • Input bandwidth (3dB): TBD
  • Full scale input voltage: TBD

 

High-Precision Analog Inputs (SDAC)

  • Input connectors: balanced, front CJT biaxial
  • Input impedance: 50 Ohm, DC coupled
  • Input bandwidth (3dB): TBD
  • Full scale input voltage: TBD

 

High-Frequency Analog Input (FADC)

  • Input connectors: single-ended, front MMCX
  • Input impedance: 50 Ohm, AC coupled
  • Input bandwidth (3dB): >1.6 GHz
  • Full scale input voltage: 1.8V pk-pk (9 dBm)

 

Clock and Trigger Signals

  • Clock distribution: CDCE18005 programmable buffer (host FPGA controlled via SPI)
  • External clock input: 50 Ohm, single-ended, AC coupled, front MMCX
  • External clock input frequency: up to 1000 MHz (default sampling rate – half the input clock frequency)
  • External clock input level: TBD
  • External clock output: 50 Ohm, single-ended, AC coupled, front MMCX
  • External clock output frequency: up to 1000MHz
  • Trigger input: 50 Ohm, single-ended, LVDS buffered to host FPGA
  • Trigger output: 50 Ohm, single-ended, LVDS buffered to host FPGA

 

Miscellaneous

  • Host FPGA connector: FMC-LPC
  • Digital I/Os: 4 single-ended 3.3V LVCMOS I/Os & 4 single-ended 2.5V LVCMOS I/Os (optional)
  • Auxiliary clocks: single-ended 3.3V LVCMOS input & output
  • LEDs: red, green, blue (host FPGA controlled via SPI)

 

Power & Dimensions

  • External power supply (required): 5.5V, Molex MX-5267-04A 2.5mm pitch SPOXTM vertical wire-to-board header
  • Power consumption (main analog inputs):
    • only high-precision channels: TBD
    • with high-speed channel: TBD
  • Dimensions: 69.0 × 95.0 mm

 

Support

  • Vivado Interface IP
  • Host FPGA Pin Description (UCF/XCF)

Ordering

  • FMC-142-S
  • FMC-142-SF

Double FMC-HPC to CXP iPass adapter

FMC-902 is a FMC-HPC to Molex CXP iPassTM adapter board, providing a flexible connection between two FPGA host boards. It contains two FMC-HPC connectors and two Molex iPass? High-Speed Channel (HSC) CXP Copper and Optical System connectors. The board passes a total number of 22 duplex channels (44 pairs) between connector types. Of this number, 16 channels are destined for MGT transceivers, and remaing 6 for other LVDS signalization. It allowes the total throughput of over 320 Gbps.

The adapter also provides some clocking resources, based on a Silicon Labs Si5338 I2C Programmable Any Frequency, Any Output Quad Clock Generator, driven by the 25MHz oscillator. Auxiliary SMA connectors allow synchronization of both cable ends.

Single FMC-HPC to CXP adapter (FMC-901) on demand.

       

 


Specification

Basic Specification

  • Dimensions: 76.5 × 139.0 mm

 

Links

 

 


Application example

Two FMC-902 boards and two 1-meter cables connecting two Xilinx VC-707 boards (test setup). Measured BER <3×10-17 (PRBS-7 pattern @ 10Gbps on 32 channels, running for 28 hours). On the right picture below: the real eye-scans for the MGT transmission channels.

    

FMC-904

Double FMC-HPC to FMC-HPC backplane

FMC-904 is an FMC-HPC to FMC-HPC backplane board, providing a rigid connection between two FPGA host boards. It contains four FMC-HPC connectors. The board passes a total number of 36 duplex channels (72 pairs) between backplane ends. Of this number, 16 channels are destined for MGT transceivers, and remaing 20 for other LVDS signalization. It allowes the total throughput of over 320 Gbps.

For every backplane end the board also provides clocking resources, based on a Silicon Labs Si5338 I2C Programmable Any Frequency, Any Output Quad Clock Generator, driven by the 25MHz oscillator. Auxiliary SMA connectors allow synchronization of both backplane ends.

Single FMC-HPC to FMC-HPC MGT backplane (FMC-903) on demand.

     


Specification

Basic Specification

  • Dimensions: 139.0 × 218.0 mm

 

Links

 


Application example

One FMC-904 board connecting two Xilinx VC-707 boards (test setup). Measured BER <3×10-17 (PRBS-7 pattern @ 10Gbps on 32 channels, running for 28 hours).  On the right picture below: the real eye-scans for the MGT transmission channels.