Quad 1Msps 20b ADC
Quad 1Msps 16b DAC
Single 2.3Ghz 500Msps 12b ADC

FMC-142 is a multi-purpose ADC/DAC board. It contains nine converters: four high-precision D/A converters (16-bit/1Msps), four high-precision A/D converters (20-bit/1Msps) and one optional fast A/D converter (500Msps/12-bit or 400Msps/14-bit, featuring extremally wide analog front end bandwidth of 2.3 GHz). The digital LVCMOS 2.5V and LVDS interfaces support FPGA Mezzanine Card FMC-LPC connector standard.

Clocking resources provide perfect synchronization to all the converters. The external clock source is required. The onboard programmable clock buffer allows generation of derivative clock frequencies and controll of the clock phases. The board is equipped with external clock input and output connectors. Thus the number of input channels may be easily increased by synchronizing multiple boards.

Auxiliary Trigger In and Trigger Out signals on MMCX connectors are passed directly to/from the host FPGA via balanced transmission lines.

The board is also equipped with a set of miscellaneous functions: 4 digital 2.5V I/Os and 4 digital 3.3V I/Os, 3 LEDs and control resources for clock buffer (frequency, phase, power-up, synchro-start and others) – all controlled via SPI interface by the host FPGA.

Board Specification

Basic Specification
  • Conversion channels: 9
  • Sampling frequency: up to 1 Msps for high-precision converters / up to 500 Msps for high-speed converter
  • Sampling resolution: 16/20 bits for high-precision converters / 12 bits for high-speed converter
  • Devices: 4x LTC2642 / 4x LTC2378 / 1x ADS5463 (optional)
  • Analog inputs/outputs: 4 HP outpurs (SDAC) / 4 HP inputs (SADC) / 1 HF input (FADC) – optional
  • THD (board): TBD
  • SFDR (board): TBD
High-Precision Analog Outputs (SDAC)
  • Output connectors: single-ended, front MMCX
  • Output impedance: 50 Ohm, DC coupled
  • Output bandwidth (3dB): TBD
  • Full scale output voltage: max +/-15V, set in factory, individually for each channel
High-Precision Analog Inputs (SADC)
  • Input connectors: balanced, front CJT biaxial
  • Input impedance: 50 Ohm, DC coupled
  • Input bandwidth (3dB): TBD
  • Full scale input voltage: TBD
High-Frequency Analog Input (FADC)
  • Input connectors: single-ended, front MMCX
  • Input impedance: 50 Ohm, AC coupled
  • Input bandwidth (3dB): >1.6 GHz
  • Full scale input voltage: 1.8V pk-pk (9 dBm)
Clock and Trigger Signals
  • Clock distribution: CDCE18005 programmable buffer (host FPGA controlled via SPI)
  • External clock input: 50 Ohm, single-ended, AC coupled, front MMCX
  • External clock input frequency: up to 1000 MHz (default sampling rate – half the input clock frequency)
  • External clock input level: TBD
  • External clock output: 50 Ohm, single-ended, AC coupled, front MMCX
  • External clock output frequency: up to 1000MHz
  • Trigger input: 50 Ohm, single-ended, LVDS buffered to host FPGA
  • Trigger output: 50 Ohm, single-ended, LVDS buffered to host FPGA
  • Host FPGA connector: FMC-LPC
  • Digital I/Os: 4 single-ended 3.3V LVCMOS I/Os & 4 single-ended 2.5V LVCMOS I/Os (optional)
  • Auxiliary clocks: single-ended 3.3V LVCMOS input & output
  • LEDs: red, green, blue (host FPGA controlled via SPI)
Power & Dimensions
  • External power supply (required): +12V, +/-6V and/or +/-16V, Molex MX-5267-10A 2.5mm pitch SPOXTM vertical wire-to-board header
  • Power consumption (main analog inputs):
    • only high-precision channels: TBD
    • with high-speed channel: TBD
  • Dimensions: 69.0 × 95.0 mm
  • Vivado Interface IP
  • Host FPGA Pin Description (UCF/XDC)



  • o – options:
    • S for slow sampling ADC/DACs (standard)
    • F for fast sampling ADC (optional)


  • FMC-142-S
  • FMC-141-SF