Single/Dual 2.3GHz 500/400MSps 12/14b ADC

FMC-141 is an advanced high-speed ADC board. It contains one or two A/D converters (500MSps/12-bit or 400MSps/14-bit), featuring extremally wide analog front end bandwidth of 2.3 GHz. The parallel digital LVDS output interface supports FPGA Mezzanine Card FMC-LPC connector standard. The optional LF analog paths (switched with relays) may be provided on demand.

Clocking resources provide users a selection of onboard sample clock frequencies. With an onboard oscillator user may select sample rates of 340, 400, 420 and 500 MSps (or another set of frequencies on demand). The onboard programmable clock buffer allows generation of derivative clock frequencies, as well as controll of the clock phases for multi-phase signal sampling mode. For the extremely precise timing the external clock may be also provided. The board is equipped with external clock input and output connectors. Thus the number of input channels may be easily increased by synchronizing multiple boards.

Trigger In and Trigger Out signals on front panel MMCX connectors are passed directly to/from the host FPGA via balanced transmission lines.

The board is also equipped with a set of miscellaneous functions: 4 digital 2.5V I/Os and 4 digital 3.3V I/Os, 3 LEDs, control resources for analog paths (relays and power-up signals), clock oscillator frequency selector, clock buffer control (frequency, phase, power-up, synchro-start and others) - all controlled via SPI interface by the host FPGA.

Board Specification

Basic Specification
  • Conversion channels: 1 or 2
  • Sampling frequency: up to 500 Msps (single channel) / up to 1000Msps (interleaved)
  • Sampling resolution: 12-bit / 14-bit
  • Devices: 2x TI's ADS5463 / ADS5474
  • Analog inputs: main HF (auxiliary LF - optional, switched by signal realys)
  • THD (board): 74 dBc
  • SFDR (board): 76 dBc
Main Analog Inputs (HF)
  • Input connectors: single-ended, front MMCX
  • Input impedance: 50 Ohm, AC coupled
  • Input bandwidth (3dB): >1.6 GHz
  • Full scale input voltage: 1.8V pk-pk (9 dBm)
Auxiliary Analog Inputs (LF, optional)
  • Input connectors: single-ended, front MMCX
  • Input impedance: 50 Ohm, AC coupled
  • Input bandwidth (3dB): TBD
  • Full scale input voltage: TBD
  • Amplifier power-up: host FPGA controlled via SPI
Clock and Trigger Signals
  • Internal clock, software selectable (host FPGA controlled via SPI): 680 / 800 / 840 / 1000 MHz
  • Clock distribution: CDCE18005 programmable buffer (host FPGA controlled via SPI)
  • External clock input: 50 Ohm, single-ended, AC coupled, front MMCX
  • External clock input frequency: up to 1000 MHz
  • External clock input level: TBD
  • External clock output: 50 Ohm, single-ended, AC coupled, front MMCX
  • External clock output frequency: up to 1000MHz (default - half the input clock frequency)
  • Trigger input: 50 Ohm, single-ended, LVDS buffered to host FPGA
  • Trigger output: 50 Ohm, single-ended, LVDS buffered to host FPGA
  • Host FPGA connector: FMC-LPC
  • Digital I/Os: 4 single-ended 3.3V LVCMOS I/Os & 4 single-ended 2.5V LVCMOS I/Os (optional)
  • Auxiliary clocks: single-ended 3.3V LVCMOS input & output
  • LEDs: red, green, blue (host FPGA controlled via SPI)
Power & Dimensions
  • External power supply (required): 5.5V, Molex MX-5267-04A 2.5mm pitch SPOXTM vertical wire-to-board header
  •  Power consumption (main analog inputs):
    • 1 channel: 5.4W
    • 2 channels: TBD
  • Dimensions: 69.0 × 95.0 mm
  • Vivado Interface IP
  • Host FPGA Pin Description (UCF/XDC)



  • n - # of channels/ADCs: 1 or 2
  • fbb - frequency/bits: 512 for ADS5463 (500Msps/12bits) or 414 for ADS5474 (400Msps/14bits)
  • in - type of inputs: H for High Frequency or HL for High and Low Frequency


  • FMC-141-1-512-H
  • FMC-141-2-414-HL


All maesurements were taken with Crystek's CCSO-914X-1000 Ultra-Low Phase Noise 1GHz SAW Clock Oscillator driving the external clock input.