Cherenkov camera

The Cherenkov Telescope Array (CTA) project is an initiative to build the next generation ground-based very high energy gamma-ray instrument. It will serve as an open observatory to a wide astrophysics community and will provide a deep insight into the non-thermal high-energy universe.

The Cherenkov Telescope Array will explore our Universe in depth in Very High Energy (VHE,  E > 10 GeV) gamma-rays and investigate cosmic non-thermal processes, in close cooperation with observatories operating at other wavelength ranges of the electromagnetic spectrum, and those using other messengers such as cosmic rays and neutrinos. The design foresees a factor of 5-10 improvement in sensitivity in the current very high energy gamma ray domain of about 100 GeV to some 10 TeV, and an extension of the accessible energy range from well below 100 GeV to above 100 TeV.

An array of many tens of telescopes will allow the detection of gamma-ray induced cascades over a large area on the ground, increasing the number of detected gamma rays dramatically, while at the same time providing a much larger number of views of each cascade. The CTA will consist of three types of telescopes with different mirror sizes in order to cover the full energy range. Among them, the high energy instruments, operating between a few TeV to 300 TeV, will consist of about 70 small (4 metre diameter) telescopes with a FoV ranging from 9.1 to 9.6 degrees.

Camera architecture

The telescope camera bears the name DigiCam. The design separates the photon detection plane (PDP) from the digital camera electronics. With such an approach, the mechanical construction of the PDP follows the needs of physics and optics (hexagonal geometry) and the construction of the digital readout and trigger systems follows the needs for a compact, standard and easily cooled electronics. However, both parts fit into one, compact enclosure, mounted on top of the telescope mast.

ADC board

The ADC board main tasks are: to digitize the analog signals of the PDP and to pre-process digitized signals and store them in digital ring buffers. Its job is also to calculate the first level trigger (L0) signals and send them continuously to the trigger board. Since the main goal of this design was to increase the level of integration, using the single-channel ADCs with parallel data output was not possible. It would take too large area of PCBs and require a high number of routing layers and FPGA pins. Thus another concept was chosen - to employ highly integrated, multi-channel A/D converters, equipped with the fast serial digital data interfaces. Using such devices releases constraints on number of PCB layers and FPGA pins. Two types of flash converters (FADC) were used: 4-channel AD9239 converter from Analog Devices and 2-channel ISLA222S25 converter from Intersil, both working at 12-bit, 250MSps.

Trigger board

The trigger board main tasks are: to receive the trigger signals from all the ADC boards within the crate (sector) and from the neighboring channels in other sectors, to calculate the second level trigger (L1) signals and send the decision over the whole digital electronics. The trigger algorithm is a highly parallelized, systolic computing structure, that calculates the event occurrence based on exceeding the threshold on the sum of L0 trigger data, counted for 7- or 19-triplet patches (neighborhoods). The board's job is also to collect the event data from all the ADC boards within the crate and send them to the central acquisition system. The 10Gb Ethernet link is used for this purpose. Thus, the main functional devices on the board are FPGA, DDR3 memory card and a number of high-speed connectors.


The backplane is a multi-layer PCB with connectors for 10 boards (9 ADC boards and 1 trigger board), and connections between them organized with a star topology, with the trigger board being the logical center (physically the trigger board is placed at backplane's right end). For each ADC board there are: four high-speed 8Gbps unidirectional channels for trigger data transmission, one low-speed 1Gbps unidirectional channel for data readout and one bidirectional 1Gbps for readout and slow control, and an additional high-performance connectivity resources for clock, synchronization and trigger transmission. There are also means for setting addresses for the crate and for each slot within the crate. The 24V DC power supply for all the boards is distributed over several backplane layers.